Details
LDPC coding is a well-known channel coding technique widely used in digital video broadcasting, wireless networking, 5G mobile communication and space data transmission. It offers improved performance over common coding schemes such as convolutional and Reed–Solomon codes, and performance matching that of Turbo codes. Good performance comes at a cost, however: LDPC encoder and decoder implementations can be demanding in terms of FPGA footprint and energy consumption.
In space data transmission for CubeSats, two differing trends can be observed. There is a growing need for high-bitrate communication links for LEO missions (e.g. Earth observation missions and high-throughput optical communication links). At the same time, there is a need for reliable, long-distance links with low resource consumption, as shown by deep space exploration missions such as MarCO, BioSentinel and LICIACube. LDPC coding is suitable for both use cases; however, the competing requirements of high bitrate and low resource usage pose a challenge for LDPC design: which one to favour, and how to balance them?
Regius has developed LDPC IP cores that are highly configurable at synthesis time, enabling a selectable trade-off between high data throughput and low FPGA resource usage. Depending on the selected codewords, our IP cores can synthesise LDPC encoders/decoders whose FPGA resource usage (FF, LUT, BRAM) varies by more than 10 times, while data throughput varies by more than 100 times. This unique solution makes it possible to tailor the LDPC coder to mission needs, offering the best FPGA resource usage for the required data throughput, or vice versa.